Storage

DFlipFlop

Class bw.storage.DFlipFlop

_images/DFlipFlop.svg

Defined in bitwise/storage/FLOP.py.

Positive edge-triggered D flip-flop.

__init__

__init__(
    data,
    clock,
    output,
    output_not
)

Construct a new positive edge-triggered D flip-flop.

Args:

  • data: An object of type Wire. The data input to the flip-flop.
  • clock: An object of type Wire or Clock. The clock input to the flip-flop.
  • output: An object of type Wire. The output of the flip-flop. Takes on the value of data on the positive edges of clock.
  • output_not: An object of type Wire. The complemented form of output.

__str__

Print out the wire values of the D flip-flop.

data: 0
clock: 0
output: 0
output_not: 0

__call__

__call__(
    data=None,
    clock=None,
    output=None,
    output_not=None
)

Force specific values on the wires of the D flip-flop.

Note that this method takes zero positional arguments; all values must be given as keyword arguments.

DFlipFlopPresetClear

Class bw.storage.DFlipFlopPresetClear

_images/DFlipFlopPresetClear.svg

Defined in bitwise/storage/FLOP.py.

Positive edge-triggered D flip-flop with asynchronous active low preset and clear.

__init__

__init__(
    data,
    preset_n,
    clear_n,
    clock,
    output,
    output_not
)

Construct a new positive edge-triggered D flip-flop with preset/clear capabilities.

Args:

  • data: An object of type Wire. The data input to the flip-flop.
  • preset_n: An object of type Wire. Presets output to 1 and output_not to 0 asynchronously if its value is 0.
  • clear_n: An object of type Wire. Clears output to 0 and output_not to 1 asynchronously if its value is 0.
  • clock: An object of type Wire or Clock. The clock input to the flip-flop.
  • output: An object of type Wire. The output of the flip-flop. Takes on the value of data on the positive edges of clock.
  • output_not: An object of type Wire. The complemented form of output.

__str__

Print out the wire values of the D flip-flop with preset/clear capabilities.

data: 0
preset_n: 0
clear_n: 0
clock: 0
output: 0
output_not: 0

__call__

__call__(
    data=None,
    preset_n=None,
    clear_n=None,
    clock=None,
    output=None,
    output_not=None
)

Force specific values on the wires of the D flip-flop with preset/clear capabilities.

Note that this method takes zero positional arguments; all values must be given as keyword arguments.

GatedDLatch

Class bw.storage.GatedDLatch

_images/GatedDLatch.svg

Defined in bitwise/storage/FLOP.py.

Gated D latch.

__init__

__init__(
    data,
    clock,
    output,
    output_not
)

Construct a new gated D latch.

Args:

  • data: An object of type Wire. The data input to the latch.
  • clock: An object of type Wire or Clock. The clock input to the latch.
  • output: An object of type Wire. The output of the latch. Takes on the value of data if the value of clock is 1.
  • output_not: An object of type Wire. The complemented form of output.

__str__

Print out the wire values of the gated D latch.

data: 0
clock: 0
output: 0
output_not: 0

__call__

__call__(
    data=None,
    clock=None,
    output=None,
    output_not=None
)

Force specific values on the wires of the gated D latch.

Note that this method takes zero positional arguments; all values must be given as keyword arguments.

GatedSRLatch

Class bw.storage.GatedSRLatch

_images/GatedSRLatch.svg

Defined in bitwise/storage/FLOP.py.

Gated SR latch.

__init__

__init__(
    set,
    reset,
    clock,
    output,
    output_not
)

Construct a new gated SR latch.

Args:

  • set: An object of type Wire. The set input to the latch.
  • reset: An object of type Wire. The reset input to the latch.
  • clock: An object of type Wire or Clock. The clock input to the latch.
  • output: An object of type Wire. The output of the latch. When the value of clock is 1, takes on the value of 1 if the value of set is 1 and the value of 0 if the value of reset is 1.
  • output_not: An object of type Wire. The complemented form of output.

__str__

Print out the wire values of the gated SR latch.

set: 0
reset: 0
clock: 0
output: 0
output_not: 0

__call__

__call__(
    set=None,
    reset=None,
    clock=None,
    output=None,
    output_not=None
)

Force specific values on the wires of the gated SR latch.

Note that this method takes zero positional arguments; all values must be given as keyword arguments.

JKFlipFlop

Class bw.storage.JKFlipFlop

_images/JKFlipFlop.svg

Defined in bitwise/storage/FLOP.py.

Positive edge-triggered JK flip-flop.

__init__

__init__(
    J,
    K,
    clock,
    output,
    output_not
)

Construct a new positive edge-triggered JK flip-flop.

Args:

  • J: An object of type Wire. The J input to the flip-flop.
  • K: An object of type Wire. The K input to the flip-flop.
  • clock: An object of type Wire or Clock. The clock input to the flip-flop.
  • output: An object of type Wire. The output of the flip-flop. On the positive edges of clock, takes on the value of 1 if the value of J is 1, takes on the value of 0 if the value of K is 1, and toggles its value if both J and K have value 1.
  • output_not: An object of type Wire. The complemented form of output.

__str__

Print out the wire values of the JK flip-flop.

J: 0
K: 0
clock: 0
output: 0
output_not: 0

__call__

__call__(
    J=None,
    K=None,
    clock=None,
    output=None,
    output_not=None
)

Force specific values on the wires of the JK flip-flop.

Note that this method takes zero positional arguments; all values must be given as keyword arguments.

JKFlipFlopPresetClear

Class bw.storage.JKFlipFlopPresetClear

_images/JKFlipFlopPresetClear.svg

Defined in bitwise/storage/FLOP.py.

Positive edge-triggered JK flip-flop with asynchronous active low preset and clear.

__init__

__init__(
    J,
    K,
    preset_n,
    clear_n,
    clock,
    output,
    output_not
)

Construct a new positive edge-triggered JK flip-flop with preset/clear capabilities.

Args:

  • J: An object of type Wire. The J input to the flip-flop.
  • K: An object of type Wire. The K input to the flip-flop.
  • preset_n: An object of type Wire. Presets output to 1 and output_not to 0 asynchronously if its value is 0.
  • clear_n: An object of type Wire. Clears output to 0 and output_not to 1 asynchronously if its value is 0.
  • clock: An object of type Wire or Clock. The clock input to the flip-flop.
  • output: An object of type Wire. The output of the flip-flop. On the positive edges of clock, takes on the value of 1 if the value of J is 1, takes on the value of 0 if the value of K is 1, and toggles its value if both J and K have value 1.
  • output_not: An object of type Wire. The complemented form of output.

__str__

Print out the wire values of the JK flip-flop with preset/clear capabilities.

J: 0
K: 0
preset_n: 0
clear_n: 0
clock: 0
output: 0
output_not: 0

__call__

__call__(
    J=None,
    K=None,
    preset_n=None,
    clear_n=None,
    clock=None,
    output=None,
    output_not=None
)

Force specific values on the wires of the JK flip-flop with preset/clear capabilities.

Note that this method takes zero positional arguments; all values must be given as keyword arguments.

RAM16x4

Class bw.storage.RAM16x4

_images/RAM16x4.svg

Defined in bitwise/storage/RAM.py.

16-word deep 4-bit wide random access memory.

__init__

__init__(
    data_bus,
    address_bus,
    write_enable,
    clock,
    output_bus
)

Construct a new 16-word deep 4-bit wide random access memory array.

Args:

  • data_bus: An object of type Bus4. The data input in write operations.
  • address_bus: An object of type Bus4. The address from which data is read from and written to.
  • write_enable: An object of type Wire. The write enable input. A value of 1 indicates a write operation, while a value of 0 indicates a read-only operation (the value on data_bus is ignored).
  • clock: An object of type Wire or Clock. The clock input.
  • output_bus: An object of type Bus4. The currently stored data in the at the address indicated by address_bus.

Raises:

  • TypeError: If either data_bus, address_bus, or output_bus is not a bus of width 4.

__str__

Print out the wire values of the random access memory array.

data_bus: (0, 0, 0, 0)
address_bus: (0, 0, 0, 0)
write_enable: 0
clock: 0
output_bus: (0, 0, 0, 0)

__call__

__call__(
    data_bus=None,
    address_bus=None,
    write_enable=None,
    clock=None,
    output_bus=None
)

Force specific values on the wires of the random access memory array.

Note that this method takes zero positional arguments; all values must be given as keyword arguments.

RAM256x4

Class bw.storage.RAM256x4

_images/RAM256x4.svg

Defined in bitwise/storage/RAM.py.

256-word deep 4-bit wide random access memory.

__init__

__init__(
    data_bus,
    address_bus,
    write_enable,
    clock,
    output_bus
)

Construct a new 256-word deep 4-bit wide random access memory array.

Args:

  • data_bus: An object of type Bus4. The data input in write operations.
  • address_bus: An object of type Bus8. The address from which data is read from and written to.
  • write_enable: An object of type Wire. The write enable input. A value of 1 indicates a write operation, while a value of 0 indicates a read-only operation (the value on data_bus is ignored).
  • clock: An object of type Wire or Clock. The clock input.
  • output_bus: An object of type Bus4. The currently stored data in the at the address indicated by address_bus.

Raises:

  • TypeError: If either data_bus or output_bus is not a bus of width 4, or if address_bus is not a bus of width 8.

__str__

Print out the wire values of the random access memory array.

data_bus: (0, 0, 0, 0)
address_bus: (0, 0, 0, 0, 0, 0, 0, 0)
write_enable: 0
clock: 0
output_bus: (0, 0, 0, 0)

__call__

__call__(
    data_bus=None,
    address_bus=None,
    write_enable=None,
    clock=None,
    output_bus=None
)

Force specific values on the wires of the random access memory array.

Note that this method takes zero positional arguments; all values must be given as keyword arguments.

RAM65536x4

Class bw.storage.RAM65536x4

_images/RAM65536x4.svg

Defined in bitwise/storage/RAM.py.

65536-word deep 4-bit wide random access memory.

__init__

__init__(
    data_bus,
    address_bus,
    write_enable,
    clock,
    output_bus
)

Construct a new 65536-word deep 4-bit wide random access memory array.

Args:

  • data_bus: An object of type Bus4. The data input in write operations.
  • address_bus: An object of type Bus16. The address from which data is read from and written to.
  • write_enable: An object of type Wire. The write enable input. A value of 1 indicates a write operation, while a value of 0 indicates a read-only operation (the value on data_bus is ignored).
  • clock: An object of type Wire or Clock. The clock input.
  • output_bus: An object of type Bus4. The currently stored data in the at the address indicated by address_bus.

Raises:

  • TypeError: If either data_bus or output_bus is not a bus of width 4, or if address_bus is not a bus of width 16.

__str__

Print out the wire values of the random access memory array.

data_bus: (0, 0, 0, 0)
address_bus: (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
write_enable: 0
clock: 0
output_bus: (0, 0, 0, 0)

__call__

__call__(
    data_bus=None,
    address_bus=None,
    write_enable=None,
    clock=None,
    output_bus=None
)

Force specific values on the wires of the random access memory array.

Note that this method takes zero positional arguments; all values must be given as keyword arguments.

RAM16x8

Class bw.storage.RAM16x8

_images/RAM16x8.svg

Defined in bitwise/storage/RAM.py.

16-word deep 8-bit wide random access memory.

__init__

__init__(
    data_bus,
    address_bus,
    write_enable,
    clock,
    output_bus
)

Construct a new 16-word deep 8-bit wide random access memory array.

Args:

  • data_bus: An object of type Bus8. The data input in write operations.
  • address_bus: An object of type Bus4. The address from which data is read from and written to.
  • write_enable: An object of type Wire. The write enable input. A value of 1 indicates a write operation, while a value of 0 indicates a read-only operation (the value on data_bus is ignored).
  • clock: An object of type Wire or Clock. The clock input.
  • output_bus: An object of type Bus8. The currently stored data in the at the address indicated by address_bus.

Raises:

  • TypeError: If either data_bus or output_bus is not a bus of width 8, or if address_bus is not a bus of width 4.

__str__

Print out the wire values of the random access memory array.

data_bus: (0, 0, 0, 0, 0, 0, 0, 0)
address_bus: (0, 0, 0, 0)
write_enable: 0
clock: 0
output_bus: (0, 0, 0, 0, 0, 0, 0, 0)

__call__

__call__(
    data_bus=None,
    address_bus=None,
    write_enable=None,
    clock=None,
    output_bus=None
)

Force specific values on the wires of the random access memory array.

Note that this method takes zero positional arguments; all values must be given as keyword arguments.

RAM256x8

Class bw.storage.RAM256x8

_images/RAM256x8.svg

Defined in bitwise/storage/RAM.py.

256-word deep 8-bit wide random access memory.

__init__

__init__(
    data_bus,
    address_bus,
    write_enable,
    clock,
    output_bus
)

Construct a new 256-word deep 8-bit wide random access memory array.

Args:

  • data_bus: An object of type Bus8. The data input in write operations.
  • address_bus: An object of type Bus8. The address from which data is read from and written to.
  • write_enable: An object of type Wire. The write enable input. A value of 1 indicates a write operation, while a value of 0 indicates a read-only operation (the value on data_bus is ignored).
  • clock: An object of type Wire or Clock. The clock input.
  • output_bus: An object of type Bus8. The currently stored data in the at the address indicated by address_bus.

Raises:

  • TypeError: If either data_bus, address_bus, or output_bus is not a bus of width 8.

__str__

Print out the wire values of the random access memory array.

data_bus: (0, 0, 0, 0, 0, 0, 0, 0)
address_bus: (0, 0, 0, 0, 0, 0, 0, 0)
write_enable: 0
clock: 0
output_bus: (0, 0, 0, 0, 0, 0, 0, 0)

__call__

__call__(
    data_bus=None,
    address_bus=None,
    write_enable=None,
    clock=None,
    output_bus=None
)

Force specific values on the wires of the random access memory array.

Note that this method takes zero positional arguments; all values must be given as keyword arguments.

RAM65536x8

Class bw.storage.RAM65536x8

_images/RAM65536x8.svg

Defined in bitwise/storage/RAM.py.

65536-word deep 8-bit wide random access memory.

__init__

__init__(
    data_bus,
    address_bus,
    write_enable,
    clock,
    output_bus
)

Construct a new 65536-word deep 8-bit wide random access memory array.

Args:

  • data_bus: An object of type Bus8. The data input in write operations.
  • address_bus: An object of type Bus16. The address from which data is read from and written to.
  • write_enable: An object of type Wire. The write enable input. A value of 1 indicates a write operation, while a value of 0 indicates a read-only operation (the value on data_bus is ignored).
  • clock: An object of type Wire or Clock. The clock input.
  • output_bus: An object of type Bus8. The currently stored data in the at the address indicated by address_bus.

Raises:

  • TypeError: If either data_bus or output_bus is not a bus of width 8, or if address_bus is not a bus of width 16.

__str__

Print out the wire values of the random access memory array.

data_bus: (0, 0, 0, 0, 0, 0, 0, 0)
address_bus: (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
write_enable: 0
clock: 0
output_bus: (0, 0, 0, 0, 0, 0, 0, 0)

__call__

__call__(
    data_bus=None,
    address_bus=None,
    write_enable=None,
    clock=None,
    output_bus=None
)

Force specific values on the wires of the random access memory array.

Note that this method takes zero positional arguments; all values must be given as keyword arguments.

RAM16x16

Class bw.storage.RAM16x16

_images/RAM16x16.svg

Defined in bitwise/storage/RAM.py.

16-word deep 16-bit wide random access memory.

__init__

__init__(
    data_bus,
    address_bus,
    write_enable,
    clock,
    output_bus
)

Construct a new 16-word deep 16-bit wide random access memory array.

Args:

  • data_bus: An object of type Bus16. The data input in write operations.
  • address_bus: An object of type Bus4. The address from which data is read from and written to.
  • write_enable: An object of type Wire. The write enable input. A value of 1 indicates a write operation, while a value of 0 indicates a read-only operation (the value on data_bus is ignored).
  • clock: An object of type Wire or Clock. The clock input.
  • output_bus: An object of type Bus16. The currently stored data in the at the address indicated by address_bus.

Raises:

  • TypeError: If either data_bus or output_bus is not a bus of width 16, or if address_bus is not a bus of width 4.

__str__

Print out the wire values of the random access memory array.

data_bus: (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
address_bus: (0, 0, 0, 0)
write_enable: 0
clock: 0
output_bus: (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)

__call__

__call__(
    data_bus=None,
    address_bus=None,
    write_enable=None,
    clock=None,
    output_bus=None
)

Force specific values on the wires of the random access memory array.

Note that this method takes zero positional arguments; all values must be given as keyword arguments.

RAM256x16

Class bw.storage.RAM256x16

_images/RAM256x16.svg

Defined in bitwise/storage/RAM.py.

256-word deep 16-bit wide random access memory.

__init__

__init__(
    data_bus,
    address_bus,
    write_enable,
    clock,
    output_bus
)

Construct a new 256-word deep 16-bit wide random access memory array.

Args:

  • data_bus: An object of type Bus16. The data input in write operations.
  • address_bus: An object of type Bus8. The address from which data is read from and written to.
  • write_enable: An object of type Wire. The write enable input. A value of 1 indicates a write operation, while a value of 0 indicates a read-only operation (the value on data_bus is ignored).
  • clock: An object of type Wire or Clock. The clock input.
  • output_bus: An object of type Bus16. The currently stored data in the at the address indicated by address_bus.

Raises:

  • TypeError: If either data_bus or output_bus is not a bus of width 16, or if address_bus is not a bus of width 8.

__str__

Print out the wire values of the random access memory array.

data_bus: (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
address_bus: (0, 0, 0, 0, 0, 0, 0, 0)
write_enable: 0
clock: 0
output_bus: (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)

__call__

__call__(
    data_bus=None,
    address_bus=None,
    write_enable=None,
    clock=None,
    output_bus=None
)

Force specific values on the wires of the random access memory array.

Note that this method takes zero positional arguments; all values must be given as keyword arguments.

RAM65536x16

Class bw.storage.RAM65536x16

_images/RAM65536x16.svg

Defined in bitwise/storage/RAM.py.

65536-word deep 16-bit wide random access memory.

__init__

__init__(
    data_bus,
    address_bus,
    write_enable,
    clock,
    output_bus
)

Construct a new 65536-word deep 16-bit wide random access memory array.

Args:

  • data_bus: An object of type Bus16. The data input in write operations.
  • address_bus: An object of type Bus16. The address from which data is read from and written to.
  • write_enable: An object of type Wire. The write enable input. A value of 1 indicates a write operation, while a value of 0 indicates a read-only operation (the value on data_bus is ignored).
  • clock: An object of type Wire or Clock. The clock input.
  • output_bus: An object of type Bus16. The currently stored data in the at the address indicated by address_bus.

Raises:

  • TypeError: If either data_bus, address_bus, or output_bus is not a bus of width 16.

__str__

Print out the wire values of the random access memory array.

data_bus: (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
address_bus: (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
write_enable: 0
clock: 0
output_bus: (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)

__call__

__call__(
    data_bus=None,
    address_bus=None,
    write_enable=None,
    clock=None,
    output_bus=None
)

Force specific values on the wires of the random access memory array.

Note that this method takes zero positional arguments; all values must be given as keyword arguments.

Register4

Class bw.storage.Register4

_images/Register4.svg

Defined in bitwise/storage/REG.py.

4-bit storage register.

__init__

__init__(
    data_bus,
    enable,
    clock,
    output_bus
)

Construct a new 4-bit storage register.

Args:

  • data_bus: An object of type Bus4. The data input to the register.
  • enable: An object of type Wire. Enables the register.
  • clock: An object of type Wire or Clock. The clock input to the register.
  • output_bus: An object of type Bus4. The output of the register. Takes on the value of data_bus on the positive edges of clock if the value of enable is 1.

Raises:

  • TypeError: If either data_bus or output_bus is not a bus of width 4.

__str__

Print out the wire values of the 4-bit storage register.

data_bus: (0, 0, 0, 0)
enable: 0
clock: 0
output_bus: (0, 0, 0, 0)

__call__

__call__(
    data_bus=None,
    enable=None,
    clock=None,
    output_bus=None
)

Force specific values on the wires of the 4-bit storage register.

Note that this method takes zero positional arguments; all values must be given as keyword arguments.

Register8

Class bw.storage.Register8

_images/Register8.svg

Defined in bitwise/storage/REG.py.

8-bit storage register.

__init__

__init__(
    data_bus,
    enable,
    clock,
    output_bus
)

Construct a new 8-bit storage register.

Args:

  • data_bus: An object of type Bus8. The data input to the register.
  • enable: An object of type Wire. Enables the register.
  • clock: An object of type Wire or Clock. The clock input to the register.
  • output_bus: An object of type Bus8. The output of the register. Takes on the value of data_bus on the positive edges of clock if the value of enable is 1.

Raises:

  • TypeError: If either data_bus or output_bus is not a bus of width 8.

__str__

Print out the wire values of the 8-bit storage register.

data_bus: (0, 0, 0, 0, 0, 0, 0, 0)
enable: 0
clock: 0
output_bus: (0, 0, 0, 0, 0, 0, 0, 0)

__call__

__call__(
    data_bus=None,
    enable=None,
    clock=None,
    output_bus=None
)

Force specific values on the wires of the 8-bit storage register.

Note that this method takes zero positional arguments; all values must be given as keyword arguments.

Register16

Class bw.storage.Register16

_images/Register16.svg

Defined in bitwise/storage/REG.py.

16-bit storage register.

__init__

__init__(
    data_bus,
    enable,
    clock,
    output_bus
)

Construct a new 16-bit storage register.

Args:

  • data_bus: An object of type Bus16. The data input to the register.
  • enable: An object of type Wire. Enables the register.
  • clock: An object of type Wire or Clock. The clock input to the register.
  • output_bus: An object of type Bus16. The output of the register. Takes on the value of data_bus on the positive edges of clock if the value of enable is 1.

Raises:

  • TypeError: If either data_bus or output_bus is not a bus of width 16.

__str__

Print out the wire values of the 16-bit storage register.

data_bus: (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
enable: 0
clock: 0
output_bus: (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)

__call__

__call__(
    data_bus=None,
    enable=None,
    clock=None,
    output_bus=None
)

Force specific values on the wires of the 16-bit storage register.

Note that this method takes zero positional arguments; all values must be given as keyword arguments.

SRLatch

Class bw.storage.SRLatch

_images/SRLatch.svg

Defined in bitwise/storage/FLOP.py.

SR latch.

__init__

__init__(
    set,
    reset,
    output,
    output_not
)

Construct a new SR latch.

Args:

  • set: An object of type Wire. The set input to the latch.
  • reset: An object of type Wire. The reset input to the latch.
  • output: An object of type Wire. The output of the latch. Takes on the value of 1 if the value of set is 1 and the value of 0 if the value of reset is 1.
  • output_not: An object of type Wire. The complemented form of output.

__str__

Print out the wire values of the SR latch.

set: 0
reset: 0
output: 0
output_not: 0

__call__

__call__(
    set=None,
    reset=None,
    output=None,
    output_not=None
)

Force specific values on the wires of the SR latch.

Note that this method takes zero positional arguments; all values must be given as keyword arguments.

TFlipFlop

Class bw.storage.TFlipFlop

_images/TFlipFlop.svg

Defined in bitwise/storage/FLOP.py.

Positive edge-triggered T flip-flop.

__init__

__init__(
    toggle,
    clock,
    output,
    output_not
)

Construct a new positive edge-triggered T flip-flop.

Args:

  • toggle: An object of type Wire. The toggle input to the flip-flop.
  • clock: An object of type Wire or Clock. The clock input to the flip-flop.
  • output: An object of type Wire. The output of the flip-flop. Toggles its value on the positive edges of clock if the value of toggle is 1.
  • output_not: An object of type Wire. The complemented form of output.

__str__

Print out the wire values of the T flip-flop.

toggle: 0
clock: 0
output: 0
output_not: 0

__call__

__call__(
    toggle=None,
    clock=None,
    output=None,
    output_not=None
)

Force specific values on the wires of the T flip-flop.

Note that this method takes zero positional arguments; all values must be given as keyword arguments.

TFlipFlopPresetClear

Class bw.storage.TFlipFlopPresetClear

_images/TFlipFlopPresetClear.svg

Defined in bitwise/storage/FLOP.py.

Positive edge-triggered T flip-flop with asynchronous active low preset and clear.

__init__

__init__(
    toggle,
    preset_n,
    clear_n,
    clock,
    output,
    output_not
)

Construct a new positive edge-triggered T flip-flop with preset/clear capabilities.

Args:

  • toggle: An object of type Wire. The toggle input to the flip-flop.
  • preset_n: An object of type Wire. Presets output to 1 and output_not to 0 asynchronously if its value is 0.
  • clear_n: An object of type Wire. Clears output to 0 and output_not to 1 asynchronously if its value is 0.
  • clock: An object of type Wire or Clock. The clock input to the flip-flop.
  • output: An object of type Wire. The output of the flip-flop. Toggles its value on the positive edges of clock if the value of toggle is 1.
  • output_not: An object of type Wire. The complemented form of output.

__str__

Print out the wire values of the T flip-flop with preset/clear capabilities.

toggle: 0
preset_n: 0
clear_n: 0
clock: 0
output: 0
output_not: 0

__call__

__call__(
    toggle=None,
    preset_n=None,
    clear_n=None,
    clock=None,
    output=None,
    output_not=None
)

Force specific values on the wires of the T flip-flop with preset/clear capabilities.

Note that this method takes zero positional arguments; all values must be given as keyword arguments.