Storage
DFlipFlop
__init__
__init__(
data,
clock,
output,
output_not
)
Construct a new positive edge-triggered D flip-flop.
Args:
data
: An object of typeWire
. The data input to the flip-flop.clock
: An object of typeWire
orClock
. The clock input to the flip-flop.output
: An object of typeWire
. The output of the flip-flop. Takes on the value ofdata
on the positive edges ofclock
.output_not
: An object of typeWire
. The complemented form ofoutput
.
__str__
Print out the wire values of the D flip-flop.
data: 0
clock: 0
output: 0
output_not: 0
__call__
__call__(
data=None,
clock=None,
output=None,
output_not=None
)
Force specific values on the wires of the D flip-flop.
Note that this method takes zero positional arguments; all values must be given as keyword arguments.
DFlipFlopPresetClear
Class bw.storage.DFlipFlopPresetClear
Defined in bitwise/storage/FLOP.py.
Positive edge-triggered D flip-flop with asynchronous active low preset and clear.
__init__
__init__(
data,
preset_n,
clear_n,
clock,
output,
output_not
)
Construct a new positive edge-triggered D flip-flop with preset/clear capabilities.
Args:
data
: An object of typeWire
. The data input to the flip-flop.preset_n
: An object of typeWire
. Presetsoutput
to 1 andoutput_not
to 0 asynchronously if its value is 0.clear_n
: An object of typeWire
. Clearsoutput
to 0 andoutput_not
to 1 asynchronously if its value is 0.clock
: An object of typeWire
orClock
. The clock input to the flip-flop.output
: An object of typeWire
. The output of the flip-flop. Takes on the value ofdata
on the positive edges ofclock
.output_not
: An object of typeWire
. The complemented form ofoutput
.
__str__
Print out the wire values of the D flip-flop with preset/clear capabilities.
data: 0
preset_n: 0
clear_n: 0
clock: 0
output: 0
output_not: 0
__call__
__call__(
data=None,
preset_n=None,
clear_n=None,
clock=None,
output=None,
output_not=None
)
Force specific values on the wires of the D flip-flop with preset/clear capabilities.
Note that this method takes zero positional arguments; all values must be given as keyword arguments.
GatedDLatch
__init__
__init__(
data,
clock,
output,
output_not
)
Construct a new gated D latch.
Args:
data
: An object of typeWire
. The data input to the latch.clock
: An object of typeWire
orClock
. The clock input to the latch.output
: An object of typeWire
. The output of the latch. Takes on the value ofdata
if the value ofclock
is 1.output_not
: An object of typeWire
. The complemented form ofoutput
.
__str__
Print out the wire values of the gated D latch.
data: 0
clock: 0
output: 0
output_not: 0
__call__
__call__(
data=None,
clock=None,
output=None,
output_not=None
)
Force specific values on the wires of the gated D latch.
Note that this method takes zero positional arguments; all values must be given as keyword arguments.
GatedSRLatch
__init__
__init__(
set,
reset,
clock,
output,
output_not
)
Construct a new gated SR latch.
Args:
set
: An object of typeWire
. The set input to the latch.reset
: An object of typeWire
. The reset input to the latch.clock
: An object of typeWire
orClock
. The clock input to the latch.output
: An object of typeWire
. The output of the latch. When the value ofclock
is 1, takes on the value of 1 if the value ofset
is 1 and the value of 0 if the value ofreset
is 1.output_not
: An object of typeWire
. The complemented form ofoutput
.
__str__
Print out the wire values of the gated SR latch.
set: 0
reset: 0
clock: 0
output: 0
output_not: 0
__call__
__call__(
set=None,
reset=None,
clock=None,
output=None,
output_not=None
)
Force specific values on the wires of the gated SR latch.
Note that this method takes zero positional arguments; all values must be given as keyword arguments.
JKFlipFlop
Class bw.storage.JKFlipFlop
Defined in bitwise/storage/FLOP.py.
Positive edge-triggered JK flip-flop.
__init__
__init__(
J,
K,
clock,
output,
output_not
)
Construct a new positive edge-triggered JK flip-flop.
Args:
J
: An object of typeWire
. The J input to the flip-flop.K
: An object of typeWire
. The K input to the flip-flop.clock
: An object of typeWire
orClock
. The clock input to the flip-flop.output
: An object of typeWire
. The output of the flip-flop. On the positive edges ofclock
, takes on the value of 1 if the value ofJ
is 1, takes on the value of 0 if the value ofK
is 1, and toggles its value if bothJ
andK
have value 1.output_not
: An object of typeWire
. The complemented form ofoutput
.
__str__
Print out the wire values of the JK flip-flop.
J: 0
K: 0
clock: 0
output: 0
output_not: 0
__call__
__call__(
J=None,
K=None,
clock=None,
output=None,
output_not=None
)
Force specific values on the wires of the JK flip-flop.
Note that this method takes zero positional arguments; all values must be given as keyword arguments.
JKFlipFlopPresetClear
Class bw.storage.JKFlipFlopPresetClear
Defined in bitwise/storage/FLOP.py.
Positive edge-triggered JK flip-flop with asynchronous active low preset and clear.
__init__
__init__(
J,
K,
preset_n,
clear_n,
clock,
output,
output_not
)
Construct a new positive edge-triggered JK flip-flop with preset/clear capabilities.
Args:
J
: An object of typeWire
. The J input to the flip-flop.K
: An object of typeWire
. The K input to the flip-flop.preset_n
: An object of typeWire
. Presetsoutput
to 1 andoutput_not
to 0 asynchronously if its value is 0.clear_n
: An object of typeWire
. Clearsoutput
to 0 andoutput_not
to 1 asynchronously if its value is 0.clock
: An object of typeWire
orClock
. The clock input to the flip-flop.output
: An object of typeWire
. The output of the flip-flop. On the positive edges ofclock
, takes on the value of 1 if the value ofJ
is 1, takes on the value of 0 if the value ofK
is 1, and toggles its value if bothJ
andK
have value 1.output_not
: An object of typeWire
. The complemented form ofoutput
.
__str__
Print out the wire values of the JK flip-flop with preset/clear capabilities.
J: 0
K: 0
preset_n: 0
clear_n: 0
clock: 0
output: 0
output_not: 0
__call__
__call__(
J=None,
K=None,
preset_n=None,
clear_n=None,
clock=None,
output=None,
output_not=None
)
Force specific values on the wires of the JK flip-flop with preset/clear capabilities.
Note that this method takes zero positional arguments; all values must be given as keyword arguments.
RAM16x4
Class bw.storage.RAM16x4
Defined in bitwise/storage/RAM.py.
16-word deep 4-bit wide random access memory.
__init__
__init__(
data_bus,
address_bus,
write_enable,
clock,
output_bus
)
Construct a new 16-word deep 4-bit wide random access memory array.
Args:
data_bus
: An object of typeBus4
. The data input in write operations.address_bus
: An object of typeBus4
. The address from which data is read from and written to.write_enable
: An object of typeWire
. The write enable input. A value of 1 indicates a write operation, while a value of 0 indicates a read-only operation (the value on data_bus is ignored).clock
: An object of typeWire
orClock
. The clock input.output_bus
: An object of typeBus4
. The currently stored data in the at the address indicated byaddress_bus
.
Raises:
TypeError
: If eitherdata_bus
,address_bus
, oroutput_bus
is not a bus of width 4.
__str__
Print out the wire values of the random access memory array.
data_bus: (0, 0, 0, 0)
address_bus: (0, 0, 0, 0)
write_enable: 0
clock: 0
output_bus: (0, 0, 0, 0)
__call__
__call__(
data_bus=None,
address_bus=None,
write_enable=None,
clock=None,
output_bus=None
)
Force specific values on the wires of the random access memory array.
Note that this method takes zero positional arguments; all values must be given as keyword arguments.
RAM256x4
Class bw.storage.RAM256x4
Defined in bitwise/storage/RAM.py.
256-word deep 4-bit wide random access memory.
__init__
__init__(
data_bus,
address_bus,
write_enable,
clock,
output_bus
)
Construct a new 256-word deep 4-bit wide random access memory array.
Args:
data_bus
: An object of typeBus4
. The data input in write operations.address_bus
: An object of typeBus8
. The address from which data is read from and written to.write_enable
: An object of typeWire
. The write enable input. A value of 1 indicates a write operation, while a value of 0 indicates a read-only operation (the value on data_bus is ignored).clock
: An object of typeWire
orClock
. The clock input.output_bus
: An object of typeBus4
. The currently stored data in the at the address indicated byaddress_bus
.
Raises:
TypeError
: If eitherdata_bus
oroutput_bus
is not a bus of width 4, or ifaddress_bus
is not a bus of width 8.
__str__
Print out the wire values of the random access memory array.
data_bus: (0, 0, 0, 0)
address_bus: (0, 0, 0, 0, 0, 0, 0, 0)
write_enable: 0
clock: 0
output_bus: (0, 0, 0, 0)
__call__
__call__(
data_bus=None,
address_bus=None,
write_enable=None,
clock=None,
output_bus=None
)
Force specific values on the wires of the random access memory array.
Note that this method takes zero positional arguments; all values must be given as keyword arguments.
RAM65536x4
Class bw.storage.RAM65536x4
Defined in bitwise/storage/RAM.py.
65536-word deep 4-bit wide random access memory.
__init__
__init__(
data_bus,
address_bus,
write_enable,
clock,
output_bus
)
Construct a new 65536-word deep 4-bit wide random access memory array.
Args:
data_bus
: An object of typeBus4
. The data input in write operations.address_bus
: An object of typeBus16
. The address from which data is read from and written to.write_enable
: An object of typeWire
. The write enable input. A value of 1 indicates a write operation, while a value of 0 indicates a read-only operation (the value on data_bus is ignored).clock
: An object of typeWire
orClock
. The clock input.output_bus
: An object of typeBus4
. The currently stored data in the at the address indicated byaddress_bus
.
Raises:
TypeError
: If eitherdata_bus
oroutput_bus
is not a bus of width 4, or ifaddress_bus
is not a bus of width 16.
__str__
Print out the wire values of the random access memory array.
data_bus: (0, 0, 0, 0)
address_bus: (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
write_enable: 0
clock: 0
output_bus: (0, 0, 0, 0)
__call__
__call__(
data_bus=None,
address_bus=None,
write_enable=None,
clock=None,
output_bus=None
)
Force specific values on the wires of the random access memory array.
Note that this method takes zero positional arguments; all values must be given as keyword arguments.
RAM16x8
Class bw.storage.RAM16x8
Defined in bitwise/storage/RAM.py.
16-word deep 8-bit wide random access memory.
__init__
__init__(
data_bus,
address_bus,
write_enable,
clock,
output_bus
)
Construct a new 16-word deep 8-bit wide random access memory array.
Args:
data_bus
: An object of typeBus8
. The data input in write operations.address_bus
: An object of typeBus4
. The address from which data is read from and written to.write_enable
: An object of typeWire
. The write enable input. A value of 1 indicates a write operation, while a value of 0 indicates a read-only operation (the value on data_bus is ignored).clock
: An object of typeWire
orClock
. The clock input.output_bus
: An object of typeBus8
. The currently stored data in the at the address indicated byaddress_bus
.
Raises:
TypeError
: If eitherdata_bus
oroutput_bus
is not a bus of width 8, or ifaddress_bus
is not a bus of width 4.
__str__
Print out the wire values of the random access memory array.
data_bus: (0, 0, 0, 0, 0, 0, 0, 0)
address_bus: (0, 0, 0, 0)
write_enable: 0
clock: 0
output_bus: (0, 0, 0, 0, 0, 0, 0, 0)
__call__
__call__(
data_bus=None,
address_bus=None,
write_enable=None,
clock=None,
output_bus=None
)
Force specific values on the wires of the random access memory array.
Note that this method takes zero positional arguments; all values must be given as keyword arguments.
RAM256x8
Class bw.storage.RAM256x8
Defined in bitwise/storage/RAM.py.
256-word deep 8-bit wide random access memory.
__init__
__init__(
data_bus,
address_bus,
write_enable,
clock,
output_bus
)
Construct a new 256-word deep 8-bit wide random access memory array.
Args:
data_bus
: An object of typeBus8
. The data input in write operations.address_bus
: An object of typeBus8
. The address from which data is read from and written to.write_enable
: An object of typeWire
. The write enable input. A value of 1 indicates a write operation, while a value of 0 indicates a read-only operation (the value on data_bus is ignored).clock
: An object of typeWire
orClock
. The clock input.output_bus
: An object of typeBus8
. The currently stored data in the at the address indicated byaddress_bus
.
Raises:
TypeError
: If eitherdata_bus
,address_bus
, oroutput_bus
is not a bus of width 8.
__str__
Print out the wire values of the random access memory array.
data_bus: (0, 0, 0, 0, 0, 0, 0, 0)
address_bus: (0, 0, 0, 0, 0, 0, 0, 0)
write_enable: 0
clock: 0
output_bus: (0, 0, 0, 0, 0, 0, 0, 0)
__call__
__call__(
data_bus=None,
address_bus=None,
write_enable=None,
clock=None,
output_bus=None
)
Force specific values on the wires of the random access memory array.
Note that this method takes zero positional arguments; all values must be given as keyword arguments.
RAM65536x8
Class bw.storage.RAM65536x8
Defined in bitwise/storage/RAM.py.
65536-word deep 8-bit wide random access memory.
__init__
__init__(
data_bus,
address_bus,
write_enable,
clock,
output_bus
)
Construct a new 65536-word deep 8-bit wide random access memory array.
Args:
data_bus
: An object of typeBus8
. The data input in write operations.address_bus
: An object of typeBus16
. The address from which data is read from and written to.write_enable
: An object of typeWire
. The write enable input. A value of 1 indicates a write operation, while a value of 0 indicates a read-only operation (the value on data_bus is ignored).clock
: An object of typeWire
orClock
. The clock input.output_bus
: An object of typeBus8
. The currently stored data in the at the address indicated byaddress_bus
.
Raises:
TypeError
: If eitherdata_bus
oroutput_bus
is not a bus of width 8, or ifaddress_bus
is not a bus of width 16.
__str__
Print out the wire values of the random access memory array.
data_bus: (0, 0, 0, 0, 0, 0, 0, 0)
address_bus: (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
write_enable: 0
clock: 0
output_bus: (0, 0, 0, 0, 0, 0, 0, 0)
__call__
__call__(
data_bus=None,
address_bus=None,
write_enable=None,
clock=None,
output_bus=None
)
Force specific values on the wires of the random access memory array.
Note that this method takes zero positional arguments; all values must be given as keyword arguments.
RAM16x16
Class bw.storage.RAM16x16
Defined in bitwise/storage/RAM.py.
16-word deep 16-bit wide random access memory.
__init__
__init__(
data_bus,
address_bus,
write_enable,
clock,
output_bus
)
Construct a new 16-word deep 16-bit wide random access memory array.
Args:
data_bus
: An object of typeBus16
. The data input in write operations.address_bus
: An object of typeBus4
. The address from which data is read from and written to.write_enable
: An object of typeWire
. The write enable input. A value of 1 indicates a write operation, while a value of 0 indicates a read-only operation (the value on data_bus is ignored).clock
: An object of typeWire
orClock
. The clock input.output_bus
: An object of typeBus16
. The currently stored data in the at the address indicated byaddress_bus
.
Raises:
TypeError
: If eitherdata_bus
oroutput_bus
is not a bus of width 16, or ifaddress_bus
is not a bus of width 4.
__str__
Print out the wire values of the random access memory array.
data_bus: (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
address_bus: (0, 0, 0, 0)
write_enable: 0
clock: 0
output_bus: (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
__call__
__call__(
data_bus=None,
address_bus=None,
write_enable=None,
clock=None,
output_bus=None
)
Force specific values on the wires of the random access memory array.
Note that this method takes zero positional arguments; all values must be given as keyword arguments.
RAM256x16
Class bw.storage.RAM256x16
Defined in bitwise/storage/RAM.py.
256-word deep 16-bit wide random access memory.
__init__
__init__(
data_bus,
address_bus,
write_enable,
clock,
output_bus
)
Construct a new 256-word deep 16-bit wide random access memory array.
Args:
data_bus
: An object of typeBus16
. The data input in write operations.address_bus
: An object of typeBus8
. The address from which data is read from and written to.write_enable
: An object of typeWire
. The write enable input. A value of 1 indicates a write operation, while a value of 0 indicates a read-only operation (the value on data_bus is ignored).clock
: An object of typeWire
orClock
. The clock input.output_bus
: An object of typeBus16
. The currently stored data in the at the address indicated byaddress_bus
.
Raises:
TypeError
: If eitherdata_bus
oroutput_bus
is not a bus of width 16, or ifaddress_bus
is not a bus of width 8.
__str__
Print out the wire values of the random access memory array.
data_bus: (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
address_bus: (0, 0, 0, 0, 0, 0, 0, 0)
write_enable: 0
clock: 0
output_bus: (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
__call__
__call__(
data_bus=None,
address_bus=None,
write_enable=None,
clock=None,
output_bus=None
)
Force specific values on the wires of the random access memory array.
Note that this method takes zero positional arguments; all values must be given as keyword arguments.
RAM65536x16
Class bw.storage.RAM65536x16
Defined in bitwise/storage/RAM.py.
65536-word deep 16-bit wide random access memory.
__init__
__init__(
data_bus,
address_bus,
write_enable,
clock,
output_bus
)
Construct a new 65536-word deep 16-bit wide random access memory array.
Args:
data_bus
: An object of typeBus16
. The data input in write operations.address_bus
: An object of typeBus16
. The address from which data is read from and written to.write_enable
: An object of typeWire
. The write enable input. A value of 1 indicates a write operation, while a value of 0 indicates a read-only operation (the value on data_bus is ignored).clock
: An object of typeWire
orClock
. The clock input.output_bus
: An object of typeBus16
. The currently stored data in the at the address indicated byaddress_bus
.
Raises:
TypeError
: If eitherdata_bus
,address_bus
, oroutput_bus
is not a bus of width 16.
__str__
Print out the wire values of the random access memory array.
data_bus: (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
address_bus: (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
write_enable: 0
clock: 0
output_bus: (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
__call__
__call__(
data_bus=None,
address_bus=None,
write_enable=None,
clock=None,
output_bus=None
)
Force specific values on the wires of the random access memory array.
Note that this method takes zero positional arguments; all values must be given as keyword arguments.
Register4
__init__
__init__(
data_bus,
enable,
clock,
output_bus
)
Construct a new 4-bit storage register.
Args:
data_bus
: An object of typeBus4
. The data input to the register.enable
: An object of typeWire
. Enables the register.clock
: An object of typeWire
orClock
. The clock input to the register.output_bus
: An object of typeBus4
. The output of the register. Takes on the value ofdata_bus
on the positive edges ofclock
if the value ofenable
is 1.
Raises:
TypeError
: If eitherdata_bus
oroutput_bus
is not a bus of width 4.
__str__
Print out the wire values of the 4-bit storage register.
data_bus: (0, 0, 0, 0)
enable: 0
clock: 0
output_bus: (0, 0, 0, 0)
__call__
__call__(
data_bus=None,
enable=None,
clock=None,
output_bus=None
)
Force specific values on the wires of the 4-bit storage register.
Note that this method takes zero positional arguments; all values must be given as keyword arguments.
Register8
__init__
__init__(
data_bus,
enable,
clock,
output_bus
)
Construct a new 8-bit storage register.
Args:
data_bus
: An object of typeBus8
. The data input to the register.enable
: An object of typeWire
. Enables the register.clock
: An object of typeWire
orClock
. The clock input to the register.output_bus
: An object of typeBus8
. The output of the register. Takes on the value ofdata_bus
on the positive edges ofclock
if the value ofenable
is 1.
Raises:
TypeError
: If eitherdata_bus
oroutput_bus
is not a bus of width 8.
__str__
Print out the wire values of the 8-bit storage register.
data_bus: (0, 0, 0, 0, 0, 0, 0, 0)
enable: 0
clock: 0
output_bus: (0, 0, 0, 0, 0, 0, 0, 0)
__call__
__call__(
data_bus=None,
enable=None,
clock=None,
output_bus=None
)
Force specific values on the wires of the 8-bit storage register.
Note that this method takes zero positional arguments; all values must be given as keyword arguments.
Register16
__init__
__init__(
data_bus,
enable,
clock,
output_bus
)
Construct a new 16-bit storage register.
Args:
data_bus
: An object of typeBus16
. The data input to the register.enable
: An object of typeWire
. Enables the register.clock
: An object of typeWire
orClock
. The clock input to the register.output_bus
: An object of typeBus16
. The output of the register. Takes on the value ofdata_bus
on the positive edges ofclock
if the value ofenable
is 1.
Raises:
TypeError
: If eitherdata_bus
oroutput_bus
is not a bus of width 16.
__str__
Print out the wire values of the 16-bit storage register.
data_bus: (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
enable: 0
clock: 0
output_bus: (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
__call__
__call__(
data_bus=None,
enable=None,
clock=None,
output_bus=None
)
Force specific values on the wires of the 16-bit storage register.
Note that this method takes zero positional arguments; all values must be given as keyword arguments.
SRLatch
__init__
__init__(
set,
reset,
output,
output_not
)
Construct a new SR latch.
Args:
set
: An object of typeWire
. The set input to the latch.reset
: An object of typeWire
. The reset input to the latch.output
: An object of typeWire
. The output of the latch. Takes on the value of 1 if the value ofset
is 1 and the value of 0 if the value ofreset
is 1.output_not
: An object of typeWire
. The complemented form ofoutput
.
__str__
Print out the wire values of the SR latch.
set: 0
reset: 0
output: 0
output_not: 0
__call__
__call__(
set=None,
reset=None,
output=None,
output_not=None
)
Force specific values on the wires of the SR latch.
Note that this method takes zero positional arguments; all values must be given as keyword arguments.
TFlipFlop
__init__
__init__(
toggle,
clock,
output,
output_not
)
Construct a new positive edge-triggered T flip-flop.
Args:
toggle
: An object of typeWire
. The toggle input to the flip-flop.clock
: An object of typeWire
orClock
. The clock input to the flip-flop.output
: An object of typeWire
. The output of the flip-flop. Toggles its value on the positive edges ofclock
if the value oftoggle
is 1.output_not
: An object of typeWire
. The complemented form ofoutput
.
__str__
Print out the wire values of the T flip-flop.
toggle: 0
clock: 0
output: 0
output_not: 0
__call__
__call__(
toggle=None,
clock=None,
output=None,
output_not=None
)
Force specific values on the wires of the T flip-flop.
Note that this method takes zero positional arguments; all values must be given as keyword arguments.
TFlipFlopPresetClear
Class bw.storage.TFlipFlopPresetClear
Defined in bitwise/storage/FLOP.py.
Positive edge-triggered T flip-flop with asynchronous active low preset and clear.
__init__
__init__(
toggle,
preset_n,
clear_n,
clock,
output,
output_not
)
Construct a new positive edge-triggered T flip-flop with preset/clear capabilities.
Args:
toggle
: An object of typeWire
. The toggle input to the flip-flop.preset_n
: An object of typeWire
. Presetsoutput
to 1 andoutput_not
to 0 asynchronously if its value is 0.clear_n
: An object of typeWire
. Clearsoutput
to 0 andoutput_not
to 1 asynchronously if its value is 0.clock
: An object of typeWire
orClock
. The clock input to the flip-flop.output
: An object of typeWire
. The output of the flip-flop. Toggles its value on the positive edges ofclock
if the value oftoggle
is 1.output_not
: An object of typeWire
. The complemented form ofoutput
.
__str__
Print out the wire values of the T flip-flop with preset/clear capabilities.
toggle: 0
preset_n: 0
clear_n: 0
clock: 0
output: 0
output_not: 0
__call__
__call__(
toggle=None,
preset_n=None,
clear_n=None,
clock=None,
output=None,
output_not=None
)
Force specific values on the wires of the T flip-flop with preset/clear capabilities.
Note that this method takes zero positional arguments; all values must be given as keyword arguments.